SRI512, 13.56 MHz short-range contactless memory chip with 512-bit EEPROM and anticollision functions
The SRI512 is a contactless memory, powered by an externally transmitted radio wave. It contains a 512-bit user EEPROM fabricated with STMicroelectronics CMOS technology. The memory is organized as 16 blocks of 32 bits. The SRI512 is accessed via the 13.56 MHz carrier. Incoming data are demodulated and decoded from the received amplitude shift keying (ASK) modulation signal and outgoing data are generated by load variation using bit phase shift keying (BPSK) coding of a 847 kHz subcarrier. The received ASK wave is 10% modulated. The data transfer rate between the SRI512 and the reader is 106 Kbit/s in both reception and emission modes. The SRI512 follows the ISO 14443-2 Type B recommendation for the radio-frequency power and signal interface.
The SRI512 is specifically designed for short range applications that need re-usable products. The SRI512 includes an anticollision mechanism that allows it to detect and select tags present at the same time within range of the reader. Using the STMicroelectronics single chip coupler, CRX14, it is easy to design a reader and build a contactless system.
The SRI512 contactless EEPROM can be randomly read and written in block mode (each block containing 32 bits). The instruction set includes the following nine commands:
● Read_block
● Write_block
● Initiate
● Pcall16
● Slot_marker
● Select
● Completion
● Reset_to_inventory
● Get_UID
The SRI512 memory is organized in three areas, as described in Table 3. The first area is a resettable OTP (one-time programmable) area in which bits can only be switched from 1 to 0. Using a special command, it is possible to erase all bits of this area to 1. The second area provides two 32-bit binary counters that can only be decremented from FFFF FFFFh to 0000 0000h, and gives a capacity of 4,294,967,296 units per counter. The last area is the EEPROM memory. It is accessible by block of 32 bits and includes an auto-erase cycle during each Write_block command.
■ ISO 14443-2 Type B air interface compliant
■ ISO 14443-3 Type B frame format compliant
■ 13.56 MHz carrier frequency
■ 847 kHz subcarrier frequency
■ 106 Kbit/second data transfer
■ 8 bit Chip_ID based anticollision system
■ 2 Count-down binary counters with automated antitearing protection
■ 64-bit Unique Identifier
■ 512-bit EEPROM with write protect feature
■ Read_block and Write_block (32 bits)
■ Internal tuning capacitor
■ 1million erase/write cycles
■ 40-year data retention
■ Self-timed programming cycle
■ 5 ms typical programming time
AC1, AC0
The pads for the Antenna Coil. AC1 and AC0 must be directly bonded to the antenna.
Input data transfer from the reader to the SRI512 (request frame)
The reader must generate a 13.56 MHz sinusoidal carrier frequency at its antenna, with enough energy to “remote-power” the memory. The energy received at the SRI512’s antenna is transformed into a supply voltage by a regulator, and into data bits by the ASK demodulator. For the SRI512 to decode correctly the information it receives, the reader must 10% amplitude-modulate the 13.56 MHz wave before sending it to the SRI512. This is represented in Figure 3. The data transfer rate is 106 Kbits/s.
Character transmission format for request frame
The SRI512 transmits and receives data bytes as 10-bit characters, with the least significant bit (b0) transmitted first. Each bit duration, an ETU (elementary time unit), is equal to 9.44 μs (1/106 kHz). These characters, framed by a start of frame (SOF) and an end of frame (EOF), are put together to form a command frame. A frame includes an SOF, commands, addresses, data, a CRC and an EOF as defined in the ISO 14443-3 Type B Standard. If an error is detected during data transfer, the SRI512 does not execute the command, but it does not generate an error frame.
Request Start of Frame
The SOF is composed of:
● one falling edge,
● followed by 10 ETUs at logic-0,
● followed by a single rising edge,
● followed by at least 2 ETUs (and at most 3) at logic-1.
Request End of Frame
The EOF is composed of:
● one falling edge,
● followed by 10 ETUs at logic-0,
● followed by a single rising edge.
Output data transfer from the SRI512 to the reader (answer frame)
The data bits issued by the SRI512 use back-scattering. Back-scattering is obtained by modifying the SRI512 current consumption at the antenna (load modulation). The load modulation causes a variation at the reader antenna by inductive coupling. With appropriate detector circuitry, the reader is able to pick up information from the SRI512. To improve loadmodulation detection, data is transmitted using a BPSK encoded, 847 kHz subcarrier frequency ƒs, and as specified in the ISO 14443-2 Type B Standard.
Character transmission format for answer frame
The character format is the same as for input data transfer (Figure 4). The transmitted frames are made up of an SOF, data, a CRC and an EOF (Figure 10). As with an input data transfer, if an error occurs, the reader does not issue an error code to the SRI512, but it should be able to detect it and manage the situation. The data transfer rate is 106 Kbits/second.
The SOF is composed of:
● followed by 10 ETUs at logic-0
● followed by 2 ETUs at logic-1
Answer end of frame
The EOF shown is composed of:
● followed by 10 ETUs at logic-0,
● followed by 2 ETUs at logic-1.
Between the request data transfer and the answer data transfer, all ASK and BPSK modulations are suspended for a minimum time of t0 = 128/ƒS. This delay allows the reader to switch from Transmission to Reception mode. It is repeated after each frame. After t0, the 13.56 MHz carrier frequency is modulated by the SRI512 at 847 kHz for a period of t1 = 128/ƒS to allow the reader to synchronize. After t1, the first phase transition generated by the SRI512 forms the start bit (‘0’) of the answer SOF. After the falling edge of the answer EOF, the reader waits a minimum time, t2, before sending a new request frame to the SRI512.
The 16-bit CRC used by the SRI512 is generated in compliance with the ISO14443 Type B recommendation. For further information, please see Appendix A. The initial register contents are all 1’s: FFFFh. The two-byte CRC is present in every request and in every answer frame, before the EOF. The CRC is calculated on all the bytes between SOF (not included) and the CRC field. Upon reception of a request from a reader, the SRI512 verifies that the CRC value is valid. If it is invalid, the SRI512 discards the frame and does not answer the reader. Upon reception of an answer from the SRI512, the reader should verify the validity of the CRC. In case of error, the actions to be taken are the reader designer’s responsibility. The CRC is transmitted with the least significant byte first and each byte is transmitted with the least significant bit first.
The SRI512 is organized as 16 blocks of 32 bits as shown in Table 3. All blocks are accessible by the Read_block command. Depending on the write access, they can be updated by the Write_block command. A Write_block updates all the 32 bits of the block.
This area contains five individual 32-bit Boolean words (see Figure 12 for a map of the area). A Write_block command will not erase the previous contents of the block as the write cycle is not preceded by an auto-erase cycle. This feature can be used to reset selected bits from 1 to 0. All bits previously at 0 remain unchanged. When the 32 bits of a block are all at 0, the block is empty, and cannot be updated any more. See Figure 13 and Figure 14 for examples of the result of the Write_block command in the resettable OTP area.
The five 32-bit blocks making up the Resettable OTP area can be erased in one go by adding an auto-erase cycle to the Write_block command. An auto-erase cycle is added each time the SRI512 detects a Reload command. The Reload command is mplemented through a specific update of the 32-bit binary counter located at block address 6.
The two 32-bit binary counters located at block addresses 5 and 6, respectively, are used to count down from 232 (4096 million) to 0. The SRI512 uses dedicated logic that only allows the update of a counter if the new value is lower than the previous one. This feature allows the application to count down by steps of 1 or more. The initial value is FFFF FFFEh in counter 5 and, FFFF FFFFh in counter 6. When the value displayed is 0000 0000h, the counter is empty and cannot be reloaded. The counter is updated by issuing the Write_block command to block address 5 or 6, depending on which counter is to be updated. The Write_block command writes the new 32-bit value to the counter block address. The counter programming cycles are protected by automated antitearing logic. This function allows the counter value to be protected in case of power down within the programming cycle. In case of power down, the counter value is not updated and the previous value continues to be stored. Blocks 5 and 6 can be write-protected using the OTP_Lock_Reg bits (block 255). Once a block has been protected, its contents cannot be modified. A protected counter block behaves like a ROM block.
The counter with block address 6 controls the Reload command used to reset the resettable
OTP area (addresses 0 to 4). Bits b31 to b21 act as an 11-bit Reload counter; whenever one of these 11 bits is updated, the SRI512 detects the change and adds an Erase cycle to the Write_block command for locations 0 to 4 (see Section 4.1: Resettable OTP area). The Erase cycle remains active until a Power-off or a Select command is issued. The SRI512’s resettable OTP area can be reloaded up to 2,047 times (211-1).
The 9 blocks between addresses 7 and 15 are EEPROM blocks of 32 bits each (36 bytes in total). (See Figure 17 for a map of the area.) These blocks can be accessed using the Read_block and Write_block commands. The Write_block command for the EEPROM area always includes an auto-erase cycle prior to the write cycle. Blocks 7 to 15 can be write-protected. Write access is controlled by the 9 bits of the OTP_Lock_Reg located at block address 255 (see Section 4.4.1: OTP_Lock_Reg for details). Once protected, these blocks (7 to 15) cannot be unprotected.
This area is used to modify the settings of the SRI512. It contains 3 registers:
OTP_Lock_Reg, Fixed Chip_ID and ST Reserved. See Figure 18 for a map of this area. A Write_block command in this area will not erase the previous contents. Selected bits can thus be set from 1 to 0. All bits previously at 0 remain unchanged. Once all the 32 bits of a block are at 0, the block is empty and cannot be updated any more.
The SRI512 is organized as 16 blocks of 32 bits as shown in Table 3. All blocks are accessible by the Read_block command. Depending on the write access, they can be updated by the Write_block command. A Write_block updates all the 32 bits of the block.
This area contains five individual 32-bit Boolean words (see Figure 12 for a map of the area). A Write_block command will not erase the previous contents of the block as the write cycle is not preceded by an auto-erase cycle. This feature can be used to reset selected bits from 1 to 0. All bits previously at 0 remain unchanged. When the 32 bits of a block are all at 0, the block is empty, and cannot be updated any more. See Figure 13 and Figure 14 for examples of the result of the Write_block command in the resettable OTP area.
The five 32-bit blocks making up the Resettable OTP area can be erased in one go by adding an auto-erase cycle to the Write_block command. An auto-erase cycle is added each time the SRI512 detects a Reload command. The Reload command is mplemented through a specific update of the 32-bit binary counter located at block address 6.
The two 32-bit binary counters located at block addresses 5 and 6, respectively, are used to count down from 232 (4096 million) to 0. The SRI512 uses dedicated logic that only allows the update of a counter if the new value is lower than the previous one. This feature allows the application to count down by steps of 1 or more. The initial value is FFFF FFFEh in counter 5 and, FFFF FFFFh in counter 6. When the value displayed is 0000 0000h, the counter is empty and cannot be reloaded. The counter is updated by issuing the Write_block command to block address 5 or 6, depending on which counter is to be updated. The Write_block command writes the new 32-bit value to the counter block address. The counter programming cycles are protected by automated antitearing logic. This function allows the counter value to be protected in case of power down within the programming cycle. In case of power down, the counter value is not updated and the previous value continues to be stored. Blocks 5 and 6 can be write-protected using the OTP_Lock_Reg bits (block 255). Once a block has been protected, its contents cannot be modified. A protected counter block behaves like a ROM block.
The counter with block address 6 controls the Reload command used to reset the resettable
OTP area (addresses 0 to 4). Bits b31 to b21 act as an 11-bit Reload counter; whenever one of these 11 bits is updated, the SRI512 detects the change and adds an Erase cycle to the Write_block command for locations 0 to 4 (see Section 4.1: Resettable OTP area). The Erase cycle remains active until a Power-off or a Select command is issued. The SRI512’s resettable OTP area can be reloaded up to 2,047 times (211-1).
The 9 blocks between addresses 7 and 15 are EEPROM blocks of 32 bits each (36 bytes in total). (See Figure 17 for a map of the area.) These blocks can be accessed using the Read_block and Write_block commands. The Write_block command for the EEPROM area always includes an auto-erase cycle prior to the write cycle. Blocks 7 to 15 can be write-protected. Write access is controlled by the 9 bits of the OTP_Lock_Reg located at block address 255 (see Section 4.4.1: OTP_Lock_Reg for details). Once protected, these blocks (7 to 15) cannot be unprotected.
The 16 bits, b31 to b16, of the System area (block address 255) are used as OTP_Lock_Reg bits in the SRI512. They control the write access to the 16 blocks 0 to 15 as follows:
● When b16 is at 0, block 0 is write-protected
● When b17 is at 0, block 1 is write-protected
● When b18 is at 0, block 2 is write-protected
● When b19 is at 0, block 3 is write-protected
● When b20 is at 0, block 4 is write-protected
● When b21 is at 0, block 5 is write-protected
● When b22 is at 0, block 6 is write-protected
● When b23 is at 0, block 7 is write-protected
● When b24 is at 0, block 8 is write-protected
● When b25 is at 0, block 9 is write-protected
● When b26 is at 0, block 10 is write-protected
● When b27 is at 0, block 11 is write-protected
● When b28 is at 0, block 12 is write-protected
● When b29 is at 0, block 13 is write-protected
● When b30 is at 0, block 14 is write-protected
● When b31 is at 0, block 15 is write-protected.
The OTP_Lock_Reg bits cannot be erased. Once write-protected, the blocks behave like ROM blocks and cannot be unprotected. After any modification of the OTP_Lock_Reg bits, it is necessary to send a Select command with a valid Chip_ID to the SRI512 in order to load the block write protection into the logic.
The SRI512 is provided with an anticollision feature based on a random 8-bit Chip_ID. Prior to selecting an SRI512, an anticollision sequence has to be run to search for the Chip_ID of the SRI512. This is a very flexible feature, however the searching loop requires time to run. For some applications, much time could be saved by knowing the value of the SRI512 Chip_ID beforehand, so that the SRI512 can be identified and selected directly without having to run an anticollision sequence. This is why the SRI512 was designed with an optional mask setting used to program a fixed 8-bit Chip_ID to bits b7 to b0 of the system area. When the fixed Chip_ID option is used, the random Chip_ID function is disabled.
All commands, data and CRC are transmitted to the SRI512 as 10-bit characters using ASK modulation. The start bit of the 10 bits, b0, is sent first. The command frame received by the SRI512 at the antenna is demodulated by the 10% ASK demodulator, and decoded by the internal logic. Prior to any operation, the SRI512 must have been selected by a Select command. Each frame transmitted to the SRI512 must start with a start of frame, followed by one or more data characters, two CRC bytes and the final end of frame. When an invalid frame is decoded by the SRI512 (wrong command or CRC error), the memory does not return any error code. When a valid frame is received, the SRI512 may have to return data to the reader. In this case, data is returned using BPSK encoding, in the form of 10-bit characters framed by an SOF and an EOF. The transfer is ended by the SRI512 sending the 2 CRC bytes and the EOF.
The SRI512 can be switched into different states. Depending on the current state of the SRI512, its logic will only answer to specific commands. These states are mainly used during the anticollision sequence, to identify and to access the SRI512 in a very short time. The SRI512 provides 6 different states, as described in the following paragraphs.
Power-off state
The SRI512 is in Power-off state when the electromagnetic field around the tag is not strong enough. In this state, the SRI512 does not respond to any command.
Ready state
When the electromagnetic field is strong enough, the SRI512 enters the Ready state. After Power-up, the Chip_ID is initialized with a random value. The whole logic is reset and remains in this state until an Initiate() command is issued. Any other command will be ignored by the SRI512.
Inventory state
The SRI512 switches from the Ready to the Inventory state after an Initiate() command has been issued. In Inventory state, the SRI512 will respond to any anticollision commands: Initiate(), Pcall16() and Slot_marker(), and then remain in the Inventory state. It will switch to the Selected state after a Select(Chip_ID) command is issued, if the Chip_ID in the command matches its own. If not, it will remain in Inventory state.
Selected state
In Selected state, the SRI512 is active and responds to all Read_block(), Write_block(), and Get_UID() commands. When an SRI512 has entered the Selected state, it no longer responds to anticollision commands. So that the reader can access another tag, the SRI512 can be switched to the Deselected state by sending a Select(Chip_ID2) with a Chip_ID that does not match its own, or it can be placed in Deactivated state by issuing a Completion() command. Only one SRI512 can be in Selected state at a time.
Deselected state
Once the SRI512 is in Deselected state, only a Select(Chip_ID) command with a Chip_ID matching its own can switch it back to Selected state. All other commands are ignored.
Deactivated state
When in this state, the SRI512 can only be turned off. All commands are ignored.
Anticollision
The SRI512 provides an anticollision mechanism that searches for the Chip_ID of each device that is present in the reader field range. When known, the Chip_ID is used to select an SRI512 individually, and access its memory. The anticollision sequence is managed by the reader through a set of commands described in Section 5: SRI512 operation:
● Initiate()
● Pcall16()
● Slot_marker().
The reader is the master of the communication with one or more SRI512 device(s). It initiates the tag communication activity by issuing an Initiate(), Pcall16() or lot_marker() command to prompt the SRI512 to answer. During the anticollision sequence, it might happen that two or more SRI512 devices respond simultaneously, so causing a collision. The command set allows the reader to handle the sequence, to separate SRI512 transmissions into different time slots. Once the anticollision sequence has completed, SRI512 communication is fully under the control of the reader, allowing only one SRI512 to transmit at a time. The Anticollision scheme is based on the definition of time slots during which the SRI512 devices are invited to answer with minimum identification data: the Chip_ID. The number of slots is fixed at 16 for the Pcall16() command. For the Initiate() command, there is no slot and the SRI512 answers after the command is issued. SRI512 devices are allowed to answer only once during the anticollision sequence. Consequently, even if there are several SRI512 devices present in the reader field, there will probably be a slot in which only one SRI512 answers, allowing the reader to capture its Chip_ID. Using the Chip_ID, the reader can then establish a communication channel with the identified SRI512. The purpose of the anticollision sequence is to allow the reader to select one SRI512 at a time. The SRI512 is given an 8-bit Chip_ID value used by the reader to select only one among up to 256 tags present within its field range. The Chip_ID is initialized with a random value during the Ready state, or after an Initiate() command in the Inventory state. The four least significant bits (b0 to b3) of the Chip_ID are also known as the Chip_slot_number. This 4-bit value is used by the Pcall16() and Slot_marker() commands during the anticollision sequence in the Inventory state.
Each time the SRI512 receives a Pcall16() command, the Chip_slot_number is given a new 4-bit random value. If the new value is 0000b, the SRI512 returns its whole 8-bit Chip_ID in its answer to the Pcall16() command. The Pcall16() command is also used to define the slot number 0 of the anticollision sequence. When the SRI512 receives the Slot_marker(SN) command, it compares its Chip_slot_number with the Slot_number parameter (SN). If they match, the SRI512 returns its Chip_ID as a response to the command. If they do not, the SRI512 does not answer. The Slot_marker(SN) command is used to define all the anticollision slot numbers from 1 to 15.
The anti-collision sequence is initiated by the Initiate() command which triggers all the SRI512 devices that are present in the reader field range, and that are in Inventory state. Only SRI512 devices in Inventory state will respond to the Pcall16() and Slot_marker(SN) anticollision commands. A new SRI512 introduced in the field range during the anticollision sequence will not be taken into account as it will not respond to the Pcall16() or Slot_marker(SN) command (Ready state). To be considered during the anticollision sequence, it must have received the Initiate() command and entered the Inventory state.
After each Slot_marker() command, there may be several, one or no answers from the SRI512 devices. The reader must handle all the cases and store all the Chip_IDs, correctly decoded. At the end of the anticollision sequence, after Slot_marker(15), the reader can start working with one SRI512 by issuing a Select() command containing the desired Chip_ID. If a collision is detected during the anticollision sequence, the reader has to generate a new sequence in order to identify all unidentified SRI512 devices in the field. The anticollision sequence can stop when all SRI512 devices have been identified.
Commands
SRI512 commands
See the paragraphs below for a detailed description of the Commands available on the SRI512.
Initiate() command
Command code = 06h – 00h
Initiate() is used to initiate the anticollision sequence of the SRI512. On receiving the Initiate() command, all SRI512 devices in Ready state switch to Inventory state, set a new 8-bit Chip_ID random value, and return their Chip_ID value. This command is useful when only one SRI512 in Ready state is present in the reader field range. It speeds up the Chip_ID search process. The Chip_slot_number is not used during Initiate() command access.
Pcall16() command
Command code = 06h – 04h
The SRI512 must be in Inventory state to interpret the Pcall16() command.
On receiving the Pcall16() command, the SRI512 first generates a new random
Chip_slot_number value (in the 4 least significant bits of the Chip_ID). Chip_slot_number can take on a value between 0 an 15 (1111b). The value is retained until a new Pcall16() or Initiate() command is issued, or until the SRI512 is powered off. The new Chip_slot_number value is then compared with the value 0000b. If they match, the SRI512 returns its Chip_ID value. If not, the SRI512 does not send any response. The Pcall16() command, used together with the Slot_marker() command, allows the reader to search for all the Chip_IDs when there are more than one SRI512 device in Inventory state present in the reader field range.
Slot_marker(SN) command
Command code = x6h
The SRI512 must be in Inventory state to interpret the Slot_marker(SN) command.
The Slot_marker byte code is divided into two parts:
● b3 to b0: 4-bit command code with fixed value 6.
● b7 to b4: 4 bits known as the Slot_number (SN). They assume a value between 1 and 15. The value 0 is reserved by the Pcall16() command.
On receiving the Slot_marker() command, the SRI512 compares its Chip_slot_number value with the Slot_number value given in the command code. If they match, the SRI512 returns its Chip_ID value. If not, the SRI512 does not send any response.
The Slot_marker() command, used together with the Pcall16() command, allows the reader to search for all the Chip_IDs when there are more than one SRI512 device in Inventory state present in the reader field range.
Select(Chip_ID) command
Command code = 0Eh
The Select() command allows the SRI512 to enter the Selected state. Until this command is issued, the SRI512 will not accept any other command, except for Initiate(), Pcall16() and Slot_marker(). The Select() command returns the 8 bits of the Chip_ID value. An SRI512 in Selected state, that receives a Select() command with a Chip_ID that does not match its own is automatically switched to Deselected state.
Completion() command
Command code = 0Fh
On receiving the Completion() command, an SRI512 in Selected state switches to Deactivated state and stops decoding any new commands. The SRI512 is then locked in this state until a complete reset (tag out of the field range). A new SRI512 can thus be accessed through a Select() command without having to remove the previous one from the field. The Completion() command does not generate a response.
All SRI512 devices not in Selected state ignore the Completion() command.
Reset_to_inventory() command
Command code = 0Ch
On receiving the Reset_to_inventory() command, all SRI512 devices in Selected state revert to Inventory state. The concerned SRI512 devices are thus resubmitted to the anticollision sequence. This command is useful when two SRI512 devices with the same 8-bit Chip_ID happen to be in Selected state at the same time. Forcing them to go through the anticollision sequence again allows the reader to generates new Pcall16() commands and so, to set new random Chip_IDs.
The Reset_to_inventory() command does not generate a response.
All SRI512 devices that are not in Selected state ignore the Reset_to_inventory() command.
Read_block(Addr) command
Command code = 08h
On receiving the Read_block command, the SRI512 reads the desired block and returns the 4 data bytes contained in the block. Data bytes are transmitted with the Least Significant byte first and each byte is transmitted with the least significant bit first. The address byte gives access to the 16 blocks of the SRI512 (addresses 0 to 15). Read_block commands issued with a block address above 15 will not be interpreted and the SRI512 will not return any response, except for the System area located at address 255. The SRI512 must have received a Select() command and be switched to Selected state before any Read_block() command can be accepted. All Read_block() commands sent to the SRI512 before a Select() command is issued are ignored.
Write_block (Addr, Data) command
Command code = 09h
On receiving the Write_block command, the SRI512 writes the 4 bytes contained in the command to the addressed block, provided that the block is available and not writeprotected. Data bytes are transmitted with the least significant byte first, and each byte is transmitted with the least significant bit first. The address byte gives access to the 16 blocks of the SRI512 (addresses 0 to 15). Write_block commands issued with a block address above 15 will not be interpreted and the SRI512 will not return any response, except for the System area located at address 255. The result of the Write_block command is submitted to the addressed block. See the following paragraphs for a complete description of the Write_block command:
● Figure 12: Resettable OTP area (addresses 0 to 4).
● Figure 15: Binary counter (addresses 5 to 6).
● Figure 17: EEPROM (addresses 7 to 15).
The Write_block command does not give rise to a response from the SRI512. The reader must check after the programming time, tW, that the data was correctly programmed. The SRI512 must have received a Select() command and be switched to Selected state before any Write_block command can be accepted. All Write_block commands sent to the SRI512 before a Select() command is issued, are ignored.
Get_UID() command
Command code = 0Bh
On receiving the Get_UID command, the SRI512 returns its 8 UID bytes. UID bytes are transmitted with the least significant byte first, and each byte is transmitted with the least significant bit first. The SRI512 must have received a Select() command and be switched to Selected state before any Get_UID() command can be accepted. All Get_UID() commands sent to the SRI512 before a Select() command is issued, are ignored.
Members of the SRI512 family are uniquely identified by a 64-bit Unique Identifier (UID). This is used for addressing each SRI512 device uniquely after the anticollision loop. The UID complies with ISO/IEC 15963 and ISO/IEC 7816-6. It is a read-only code, and comprises (as summarized in Figure 49):
● an 8-bit prefix, with the most significant bits set to D0h
● an 8-bit IC manufacturer code (ISO/IEC 7816-6/AM1) set to 02h (for STMicroelectronics)
● a 6-bit IC code set to 00 0110b = 6d for SRI512
● a 42-bit unique serial number
After power-on, the SRI512 is in the following state:
● It is in the low-power state.
● It is in Ready state.
● It shows highest impedance with respect to the reader antenna field.
● It will not respond to any command except Initiate().
Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
